This invention relates to high voltage semiconductor devices such as diodes and transistors in which a diode PN junction or a transistor collector-base junction must withstand applied voltages in the range from several hundred volts to several thousand volts. This invention relates more particularly to practical means of preventing premature reverse junction breakdown voltage below the theoretical breakdown value. Such premature breakdown is caused by peaking of electric fields at the surface of the single crystal semiconductor material. The peaking of the electric field is caused by impurities on the surface of or within a passivation layer protecting the semiconductor surface. However, even for impurity-free passivation layers, premature reverse breakdown may occur because of spurious charge migration and concentration on the surface of the passivation layer and resulting formation of peak electric fields along the passivation layer surface. Additionally, for close spacing of guard rings or junction overlay metal, there exists a problem of arcing caused by high electric fields at the surface of the oxide passivation layer. Arcing may cause reliability problems, including metal failure, and is customarily suppressed by subsequent organic oxide passivation layers which often have harmful effects on junction breakdown voltages. Also, spurious surface charge concentrations on the surface of the first passivation layer may, depending on their location, cause a shortening or extending of the depletion layer of the subject PN junction, thereby decreasing or completely eliminating the desired effects of annular rings. Surface charge concentrations of a particular polarity may also cause inversion of the underlying semiconductor material, possibly causing the formation of parasitic FET devices which appear as "sneak" paths. The undesired inversion of semiconductor material at the oxide-semiconductor interface may be suppressed by reducing the magnitude of the electric field across the oxide, which in turn may be accomplished by providing an appropriate potential to the surface of the oxide overlying the critical region where inversion may occur. The suppression of such sneak paths by extensions of metalization over the oxide of critical areas to set the oxide surface potential to desired values may be difficult, especially in integrated circuit structures, because of limited interconnection layout freedom.
High resistivity films overlying the subject passivation layer, and electrically contacting the semiconducotr material on both sides of the semiconductor junction, have been used to neutralize charges accumulated on the surface of the passivation layer, thereby reducing peaking of surface electric fields and the resulting arcing. Such films are described in co-pending U.S. Pat. application Ser. No. 85,638 entitled "High Voltage Passivation" filed Oct. 30, 1970, by the same inventor and assigned to the same assignee. The high resistivity film must achieve a sheet resistance of approximately 10.sup.8 -10.sup.10 ohms per square in order to provide the charge neutralization without causing excessive leakage currents at high operating voltages. Polycrystalline silicon films have been utilized to obtain such high sheet resistances. However, it has been found that the high resistivity of the polycrystalline silicon films used in this manner experience a decrease in resistivity of several orders of magnitude after aging or subsequent processing steps. It is thought that this degradation is caused mainly by contamination of the film by moisture and other impurities from subsequent ambients or organic passivation layers. Such a reduction in resistivity causes unacceptably high leakage currents. Diffused annular guard rings surrounding and spaced from the semiconductor junction have been used to interrupt the electric field in the depletion region, thereby reducing the peak values of electric fields in the depletion region. As a result the reverse breakdown voltage is increased.